2025/12/5
Masood Mehrabian

Masood Mehrabian

Academic rank: Associate Professor
ORCID:
Education: PhD.
H-Index:
Faculty: Faculty of Basic Sciences
ScholarId:
E-mail: masood.mehrabian [at] yahoo.com
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Research

Title
Built-in potential engineering via C60 buffer layer for high-performance CsSnGeI3 QD/CsSnBr3 hybrid perovskite solar cells
Type
JournalPaper
Keywords
Double absorber solar cell; SCAPS-1D; Fullerene buffer layer; CsSnBr3; CsGeSnI3; Quantum dots
Year
2025
Journal JOURNAL OF PHYSICS AND CHEMISTRY OF SOLIDS
DOI
Researchers Masood Mehrabian ، Pourya Norouzzadeh ، Rouhangiz Yahyabonyad ، Asmet N. Azizova ، Omid Akhavan

Abstract

In this study, we systematically investigated a dual-absorber solar-cell architecture under standard AM 1.5 (1- sun) illumination at 300 K using the SCAPS-1D simulation tool. The device configuration comprised an inorganic perovskite material, CsSnBr3, as the primary light-absorbing layer, followed by a secondary absorber layer composed of CsGeSnI3 quantum dots (QDs). The investigation primarily focused on evaluating the influence of a fullerene (C60) interfacial buffer layer on the photovoltaic performance metrics of the device, including overall power conversion efficiency (PCE), fill factor (FF), short-circuit current density (JSC), and open-circuit voltage (VOC) within the FTO/TiO2/CsSnBr3/CsGeSnI3 QD/P3HT/Ag device structure. Incorporation of the C60 layer as an electron acceptor enhanced charge-carrier separation by inducing a favorable built-in electric field, which in turn facilitated more efficient charge extraction and transport and led to a marked improvement in power conversion efficiency (PCE). To further elucidate the role of the buffer layer, additional simulations were per- formed, capacitance-voltage (C–V) study, built-in electric field analyzing, carrier recombination and generation. An optimization study of the C60 layer thickness showed that tuning this interfacial buffer to 300 nm yields a maximum power-conversion efficiency of 20.35 %, indicating the critical influence of layer thickness on device performance.